طراحی و شبیه سازی حافظه چهار ترانزیستوری و دو ممریستوری با کمترین توان مصرفی و حاصلضرب تاخیر در توان

نوع مقاله : مقاله پژوهشی

نویسندگان

1 دانشکده مهندسی برق- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران

2 مرکز تحقیقات ریز شبکه های هوشمند- واحد نجف آباد، دانشگاه آزاد اسلامی، نجف آباد، ایران

چکیده

ممریستور به­عنوان عنصر اساسی حافظه­های اصلی یا پنهان SRAM و DRAM، می­تواند به­صورت موثری زمان راه­اندازی و توان مصرفی مدارها را کاهش دهد. غیر فرار بودن، چگالی بالای مدار نهایی و کاهش حاصل­ضرب تاخیر در توان مصرفی PDp از حقایق قابل توجه مدارهای ممریستوری است که منجر به پیشنهاد سلول حافظه شامل چهار ترانزیستور و دو ممریستور (4T2M) در این مقاله شده است. به­منظور شبیه­سازی سلول حافظه پیشنهادی، طول ممریستورها 10 نانومتر و مقاومت حالت­های روشن و خاموش آنها به­ترتیب 250 اهم و 10 کیلو اهم انتخاب شده است. همچنین، ترانزیستورهای MOS سلول نیز توسط مدل CMOS PTM 32 نانومتر شبیه­سازی شده­اند. شبیه­سازی در نرم­افزار اچ-اسپایس و با تغذیه یک ولت و مقایسه آن با دو سلول شش ترانزیستوری متعارف (6T) و دو ترانزیستوری-دو ممریستوری (2T2M) نشان می­دهد که استفاده از ممریستور سبب غیر فرار شدن سلول­ حافظه پیشنهادی و سلول 2T2M در زمان قطع  ولتاژ تغذیه شده است، ضمن آن که مصرف توان مدار پیشنهادی نسبت به مدار 6T و 2T2M به ترتیب 8/99 درصد و 2/57 درصد کاهش یافته و حاصل ضرب متوسط تاخیر در توان نیز به ترتیب 4/99 درصد و 7/26 درصد بهبود یافته است؛ هرچند تاخیر نوشتن این سلول و سلول  2T2Mنسبت به سلول 6T به ترتیب 400 درصد و 218 درصد افزایش یافته است. 

کلیدواژه‌ها

موضوعات


عنوان مقاله [English]

Design and Simulation of 4 Transistors and 2 Memristors Memory with the Least Power and Power-Delay Product

نویسندگان [English]

  • Keramat Karami 1
  • Sayed Mohammad Ali Zanjani 2
  • Mehdi Dolatshahi 1
1 Department of Electrical Engineering- Najafabad Branch- Islamic Azad University- Najafabad, Iran
2 Smart Microgrid Research Center- Najafabad Branch, Islamic Azad University, Najafabad, Iran
چکیده [English]

Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of memristor circuits, which has led to the suggestion of a memory cell including and four transistors and two memristors (4T2M) in this paper. In order to simulate the proposed memory cell, the length of memristors has been selected 10 nm, and their on/off state resistors have been selected 250 Ω and 10 KΩ respectively. In addition, the proposed memory cell MOS transistors are simulated by the 32 nm CMOS PTM model. Simulation in the HSPICE software with 1V supply voltage and comparison with two conventional six-transistor (6T) and two transistors-two memory (2T2M) cells show that the use of memristors has made the proposed memory cell and 2T2M cell non-volatile. Moreover, the power consumption of the proposed circuit has decreased by 99.8% and 57.2%, compared to the previous two circuits respectively, and the power average delay product has also improved by 99.4% and 26.7%, respectively; however, the writing delay of this cell and 2T2M cell increased by 400% and 218% compared to 6T cell, respectively.

کلیدواژه‌ها [English]

  • Non-Volatile Memory
  • Memristor
  • 4T2M cell
  • Power Delay Product
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