نیم جمع کننده DCVS سه مقداری با استفاده از تقویت کننده‌های توکار

نوع مقاله : مقاله پژوهشی

نویسندگان

1 گروه مهندسی کامپیوتر - دانشکده فنی و مهندسی - واحد تهران غرب، دانشگاه آزاد اسلامی، تهران، ایران

2 گروه مهندسی کامپیوتر - واحد شهرقدس، دانشگاه آزاد اسلامی، تهران، ایران

چکیده

منطق DCVS یکی از معروف‌ترین روش‌های طراحی مدارهای الکترونیکی است، که یک ساختار مستحکم ایجاد می‌کند. بعلاوه، در این منطق طراحی، دو خروجی که مکمل یکدیگر هستند به‌طور همزمان تولید می‌شوند. این منطق کاربردها و ویژگی‌های زیادی دارد. در این مقاله با استفاده از سه روش مشابه، نیم جمع­کننده‌های DCVS سه مقداری جدید ارائه می‌شوند، که کارآمدی آنها به ویژه در مواقع اتصال آبشاری مدارها نمایان می‌گردد. وجود این مدارها برای طراحی مدارهای بزرگتر محاسباتی حیاتی است. در سومین و اصلی‌ترین روش پیشنهادی، به­جای استفاده از معکوس­کننده‌های سه مقداری که توان ایستای قابل ملاحظه‌ای مصرف می‌کنند، از تقویت­کننده‌های دودویی کم مصرف توکار به­­منظور تقویت سیگنال و افزایش قابلیت راندن مدارهای DCVS استفاده شده است. نتایج شبیه­سازی با استفاده از نرم افزار اچ-اسپایس و کتابخانه ترانزیستورهای نانو لوله کربنی با طول کانال 32 نانومتر نشان می‌دهد که استفاده از تقویت­کننده‌های دودویی نسبت به معادل سه مقداری موجب افزایش سرعت تا 8/21 درصد و کاهش توان مصرفی تا 7/6 درصد در یک بستر تست واقعی می‌گردد. همچنین، آخرین طرح پیشنهادی با سه نیم جمع­کننده سه مقداری دیگر نیز مقایسه شده است، که طرح جدید سرعت بالاتری از تمام آنها دارد. در مقایسه با نیم جمع­کننده DCVS قبلی، مدار پیشنهادی هم از لحاظ سرعت، و هم از لحاظ مصرف توان و انرژی عملکرد بهتری دارد.

کلیدواژه‌ها

موضوعات


عنوان مقاله [English]

Ternary DCVS Half Adder with Built-in Boosters

نویسندگان [English]

  • Naghmeh Dehabadi 1
  • Reza Faghih Mirzaee 2
1 Department of Computer Engineering- West Tehran Branch, Islamic Azad University, Tehran, Iran
2 Department of Computer Engineering- Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran
چکیده [English]

Differential Cascode Voltage Switch (DCVS) is one of the most well-known logic styles, which forms a robust structure. In addition, two complementary outputs are produced in this logic style at the same time. It has several unique attributes and different applications. This paper presents three comparable methods to design some ternary half adders, whose efficiencies are superior especially when they are put one after another in a cascading scenario. These cells are essential for the realization of larger arithmetic circuits. In the third proposed method, instead of ternary inverters, which consume considerable static power, built-in low-power binary boosters are exploited to reinforce driving power of the DCVS circuits. Simulation results by HSPICE and 32 nm Carbon Nanotube Field Effect Transistor (CNFET) technology demonstrate that the new adder cell with binary boosters operates 21.8% faster and consume 6.7% less power than the cell with ternary inverters in a real test bed. Furthermore, the final design is compared with three other ternary half adders. The new design is faster than all of them, and also consumes less power and energy than the previous DCVS half adder.

کلیدواژه‌ها [English]

  • DCVSL
  • Ternary Logic
  • Ternary Half Adder
  • Binary Booster
  • CNFET
[1] N.H.E. Weste, D.M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Addison-Wesley, Boston, Massachusetts, 2011.
[2] L.G. Heller, W.R. Griffin, J.W. Davis, N.G. Thoma, “Cascode voltage switch logic: A differential CMOS logic family”, Proceeding of the IEEE/ISSCC, pp. 16-17, San Francisco, USA, Feb. 1984 (doi: 10.1109/ISSCC.1984.1156629).
[3] K.M. Chu, D.I. Pulfrey, “A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic”, IEEE Journal of Solid-State Circuits, vol. 22, no.4, pp. 528-532, Aug. 1987 (doi: 10.1109/JSSC.1987.1052767).
[4] P. Bajpai, N. Pandey, K. Gupta, J. Panda, “LECTOR incorporated differential cascode voltage swing logic (L-DCVSL)”, Analog Integrated Circuits and Signal Processing, vol. 100, no. 1, pp. 221-234, July 2019 (doi: 10.1007/s10470-019-01466-2).
[5] R.K. Montoye, “Testing scheme for differential cascode voltage switch circuits”, IBM Technical Disclosure Bulletin, vol. 27, no. 10B, pp. 6148-6152, 1985.
[6] D.A. Rennels, H. Kim, “Concurrent error detection in self-timed VLSI”, Proceeding of the IEEE/FTCS, Austin, USA, pp. 96-105, June 1994 (doi: 10.1109/FTCS.1994.315653).
[7] Y. Kang, J. Kim, S. Kim, E. Jang, J.W. Jeong, K.R. Kim, S. Kang, “A novel ternary multiplier based on ternary CMOS compact model”, Proceeding of the IEEE/ISMVL, Novi Sad, Serbia, pp. 25-30, May 2017 (doi: 10.1109/ISMVL.2017.52).
[8] M. Kumm, O. Gustafsson, M. Garrido, P. Zipf, “Optimal single constant multiplication using ternary adders”, IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 65, no. 7, pp. 928-932, July 2018 (doi: 10.1109/TCSII.2016.2631630).
[9] M. Toulabinejad, M. Taheri, K. Navi, N. Bagherzadeh, “Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology”, Microelectronics Journal, vol. 90, pp. 267-277, Aug. 2019 (doi: 10.1016/j.mejo.2019.05.010).
[10] A. Doostaregan, A. Abrishamfar, “Evaluating a methodology for designing CNFET-based ternary circuits”, Circuits, Systems, and Signal Processing, 2020 (In Press) (doi: 10.1007/s00034-020-01400-2).
[11] S. Lin, Y.B. Kim, F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits”, IEEE Trans. on Nanotechnology, vol. 10, no. 2, pp. 217-225, Mar. 2011 (doi: 10.1109/TNANO.2009.2036-845).
[12] A. Saha, N.D. Singh, “Systematic design strategy for DPL-based ternary logic circuit”, International Journal of Nanoparticles, vol. 12, no. 1-2, pp. 3-16, 2020 (doi: 10.1504/IJNP.2020.10027790).
[13] G. Hang, X. Zhou, “Novel CMOS static ternary logic using double pass-transistor logic”, Proceeding of the ICISE, Hangzhou, China, pp. 1333-1336, Dec. 2010 (doi: 10.1109/ICISE.2010.5689867).
[14] S. Rezaie, R.F. Mirzaee, K. Navi, O. Hashemipour, “From static ternary adders to high-performance race-free dynamic ones”, The Journal of Engineering, vol. 2015, no. 12, pp. 371-382, Dec. 2015 (doi: 10.1049/jo-e.2015.0119).
[15] R.F. Mirzaee, T. Nikoubin, K. Navi, O. Hashemipour, “Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic”, Microelectronics Jounal, vol. 44. No. 12, pp. 1238-1250, Dec. 2013 (doi: 10.1016/j.mejo.2013.08.010).
[16] N. Azimi, R.F. Mirzaee, K. Navi, A.M. Rahmani, “Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source”, IET Computers & Digital Techniques, 2020 (In Press) (doi: 10.1049/iet-cdt.2019.0216).
[17] H. Lee, G.E. Sobelman, “New XOR/XNOR and full adder circuits for low voltage, low power applications”, Microelectronics Journal, vol. 29, no. 8, pp. 509-517, Aug. 1998 (doi: 10.1016/S0026-2692(97)00120-1).
[18] K. Navi, O. Kavehei, M. Ruholamini, A. Sahafi, S. Mehrabi, N. Dadkhahi, “Low-power and high-performance 1-bit CMOS full adder cell”, Journal of Computers, vol. 3, No. 2, pp. 48-54, Feb. 2008 (doi: 10.4304/jcp.3.2.48-54).
[19] S.D. Mohammadi, R.F. Mirzaee, K. Navi, “Partial product generation for unbalanced ternary signed multiplication”, International Journal of High Performance Systems Architecture, vol. 8, no. 4, pp. 238-249, 2019 (doi: 10.1504/IJHPSA.2019.104952) .
[20] A.B. Rahin, V.B. Rahin, “A new 2-input CNTFET-based XOR cell with ultra-low leakage power for low-voltage and low-power full adders”, Journal of Intelligent Procedures in Electrical Technology, vol.10 , no. 37, pp. 13-22, Spring 2019 (in Persian).
[21] A.K. Kureshi, M. Hasan, “Performance comparison of CNFET- and CMOS-based 6T SRAM cell in deep submicron”, Microelectronics Journal, vol. 40, no. 6, pp. 979-982, June 2009 (doi: 10.1016/j.mejo.2008.11.062).
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)55(
[22] G. Cho, Y.B. Kim, F. Lombardi, “Assessment of CNTFET based circuit performance and robustness to PVT variations”, Proceeding of the IEEE/MWSCAS, Cancun, Mexico, pp. 1106-1109, Aug. 2009 (doi: 10.1109/MWSCAS.2009.5235961).
[23] R.F. Mirzaee, K. Navi, N. Bagherzadeh, “High-efficient circuits for ternary addition”, VLSI Design, vol. 2014, article ID 534587, pp. 1-15, 2014 (doi: 10.1155/2014/534587).
[24] J. Deng, Device Modeling and Circuit Performance Evaluation for Nanoscale Devices: Silicon Technology Beyond 45 nm Node and Carbon Nanotube Field Effect Transistors, Ph.D. Thesis, Stanford University, 2007.
[25] E.E. Nigussie, Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects, Ph.D. Thesis, University of Turku, 2010.
[26] T. Sakurai, “Perspectives on power-aware electronics,” Proceeding of the IEEE/ISSCC, San Francisco, USA, pp. 26-29, Feb. 2003 (doi: 10.1109/ISSCC.2003.1234195).
[27] A.P. Dhande, V.T. Ingole, V.R. Ghiye, Ternary Digital System: Concepts and Applications, SM Online Publishers, 2014.
[28] M.H. Moaiyeri, A. Doostaregan, K. Navi, “Design of energy-efficient and robust ternary circuits for nanotechnology”, IET Circuits, Devices & Systems, vol. 5, no. 4, pp. 285-296, July 2011 (doi: 10.1049/iet-cds.2010.0340).
[29] H. Inokawa, A. Fujiwara, Y. Takahashi, “A multiple-valued logic with merged single-electron and MOS transistors”, International Electron Devices Meeting Technical Digest, Washington, USA, pp. 7.2.1-7.2.4, Dec. 2001 (doi: 10.1109/IEDM.2001.979453).
[30] R.F. Mirzaee, M.S. Daliri, K. Navi, N. Bagherzadeh, “A single parity-check digit for one trit error detection in ternary communication systems: Gate-level and transistor-level designs”, Journal of Multiple-Valued Logic and Soft Computing, vol. 29, no. 3-4, pp. 303-326, Aug. 2017.
[31] Stanford CNFET Model, available at: https://nano.stanford.edu/model.php
[32] T. Sharma, L. Kumre, “CNTFET-based design of ternary arithmetic modules”, Circuits, Systems, and Signal Processing, vol. 38, no. 10, pp. 4640-4666, Oct. 2019 (doi: 10.1007/s00034-019-01070-9).
[33] M. Bastami, and R.F. Mirzaee, “Integration of CTL, PTL, and DCVSL for designing a novel fast ternary half adder”, The CSI Journal on Computer Science and Engineering, vol. 15, no. 1, pp. 15-21, Summer 2017.