D. Aksin, Devrim, M.A. Al-Shyoukh, F. Maloberti, "A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage", Proceedings of the IEEE/CICC, San Jose, CA, USA, Sep. 2005.
 T.S. Lee, C.C. Lu, "Design technique for low-voltage high-speed pseudo-differential CMOS track-and-hold circuit with low hold pedestal", Electronics Letters, Vol. 40, No.9, April 2004.
 T.S. Lee, C.C. Lu, "A 1.5-v 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal", IEEE Trans. on Circuits and System, Vol. 52, No. 9, 2005.
 M. sadollahy, K. Hadidi, "High-speed highly-linear CMOS S/H circuit", Proceeding of the IEEE/ICCCE, pp. 550–553, Kuala Lumpur, Malaysia, May 2008.
 A. Boni, A. Pierazzi, and C. Morandi. "A 10-b 185-MS/s track-and-hold in 0.35-/spl mu/m CMOS", IEEE Journal of Solid-State Circuits, Vol. 36, No. 2, 2001.
 Y. Sugimoto, D.G. Haigh, "A current-mode circuit with a linearized input V/I conversion scheme and the realization of a 2/2.5V operational, 100MS/s, MOS SHA", IEEE Trans. on Circuits and Systems, Vol. 55, No. 8, pp. 2178–2187, Sep. 2008.
 M. Mousazadeh, K.H. Hadidi, A. Khoei, "A novel open-loop high-speed CMOS sample-and-hold", AEU International Journal of Electronics and Communications, Vol. 62, No. 8, pp. 588–596, Sep. 2008.
 L. Schillaci, A. Baschirotto, R. Castello, "A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz", IEEE Journal of Solid-State Circuits, Vol. 32, pp. 926–932, 1997.
 G.K. Balachandran, P.E. Allen, "Fully differential switched-current memory cell with low charge-injection errors", IEE Proceedings Circuits Devices and Systems, Vol. 148, No. 3, pp.157–163, Jun. 2001.
 C. Sawigun, W.A. Serdijn, "Analysis and design of a low-voltage, low-power, high-precision, class-AB current-mode subthreshold CMOS sample and hold circuit", IEEE Trans. on Circuits and Systems, Vol. 58, No. 7, pp. 1615–1626, July 2011.
 A. Abolhasani, M. Tohidi, K. Hadidi. A. Khoei, "A new high-speed, high-resolution open-loop CMOS sample and hold", Analog Integrated Circuits and Systems, Springer, Vol. 78, No. 2, pp. 409–419, Feb. 2014.
 M. Mousazadeh, K.H. Hadidi, A. Khoei, "A novel open-loop high-speed CMOS sample-and-hold", AEU-International Journal of Electronics and Communications 62.8, 2008.
 T.M. Khanshan, M. Nematzadeh, K. Hadidi. A. Khoei, Z.D. Kozehkanani, J. Sobhi, "Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs", Analog Integrated Circuits and Systems, Springer, Vol. 88, No. 1, pp. 23–30, July 2016.
 T.S. Lee, C.C. Lu, C.C. Ho "A 330MHz 11 bit 26.4 mW CMOS low-hold-pedestal fully differential sample-and-hold circuit", VLSI Design, Automation and Test, IEEE International Symposium on. IEEE, 2008.
 M. Mousazadeh, K. Hadidi, A. Khoei, "A highly linear open-loop high-speed CMOS sample-and-hold", Proceeding of the IEEE/ APCCAS, pp. 228 – 231, 2010.